1. Field of the Invention
The present invention relates to test devices, and more particularly, to a test device for detecting alignment of deep trench capacitors and word lines in DRAM devices, as well as a test method thereof and a semiconductor device using the same.
2. Description of the Related Art
FIG. 1 is a layout of conventional deep trench capacitors in a memory device, and FIG. 2 is a cross-section of FIG. 1 along line AA. However, as shown in FIG. 2, if word line masks and deep trench capacitors are not aligned accurately, the buried strap junction A extending from the deep trench capacitor 10 may be too close to adjacent capacitors and induce a secondary leakage current. Thus, the adjacent memory cells may experience current leakage and cell failure, reducing process yield, if active area masks and deep trench capacitors are not aligned accurately.
It is therefore an object of the present invention to detect alignment of word lines and deep trench capacitors in DRAM devices.
According to the above mentioned objects, the present invention provides a test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices.
In the test device of the present invention, parallel first and second bar-type deep trenches capacitors are disposed in the scribe line region. The first and second bar-type deep trenches capacitors extend to the first and second pairs of memory cells in memory region adjacent to the first active area respectively. The first and second bar-type deep trenches capacitors are electrically coupled to bit line contacts of the first and second pairs of memory cells respectively. First and second transistors have sources coupled to the first and second bar-type deep trenches capacitors respectively. A first bit line contact is electrically coupled to drains of the first and second transistors.
According to the present invention, a method for detecting alignment of the deep trench capacitors and word lines in the DRAM devices includes the following steps. First, a wafer with at least one scribe line region and at least one memory region is provided. Then, a plurality of pairs of memory cells in the memory region and at least one test device in the scribe line region are formed simultaneously. Both the memory region and the scribe region have bit line contacts, deep trench capacitors, and word lines. A first resistance between the first bit line contact and the bit line contact of the first pair of memory cells in the test device is measured. A second resistance between the second bit line contact and the bit line contact of the second pair of memory cells in the test device is measured. Next, alignment of the first and second bar-type deep trenches capacitors and the word lines in the test device is determined according to the first resistance and the second resistance. Finally, alignment of the deep trench capacitors and word lines in the memory regions is determined according to alignment of the first and second bar-type deep trenches capacitors and word lines in the test device.